XCZU5EV / AD9361
2×2 MIMO SDR Carrier Board
A Zynq UltraScale+ MPSoC carrier board built around the Analog Devices AD9361 RF transceiver — a switched six-band RF front end, onboard Wi-Fi/BT and GNSS, DDR4 and dual-port USB debug, all on a single compact PCB.
Board specifications
Downloads
Full schematics, block diagram, and bill of materials for this board.
Front and bottom edge connectors
Reading directly off the board's silkscreen — what's actually populated on this unit.
Top edge — RF & antenna
Bottom edge — power, data & debug
Simplified block diagram
How the major subsystems connect around the MPSoC.
Processing subsystem
| Ref | Part | Function |
|---|---|---|
| U5 | Zynq UltraScale+ MPSoC (XCZU5EV, BGA784) | Main SoC — quad-core ARM Cortex-A53 application processor, dual-core Cortex-R5 real-time processor, and FPGA programmable logic fabric. LVDS TX/RX lanes connect directly to the AD9361 for baseband I/Q streaming. |
| U50 | TCM811TERCTR | Voltage supervisor generating the PS power-on-reset signal. |
| SW1 | Tactile switch | Manual system reset. |
| SW2 | 4-position DIP switch | Sets PS_MODE[3:0] boot-source pins (QSPI / SD / JTAG boot select). |
| J6 | 6-pin 2.54 mm header | JTAG: VREF, GND, TCK, TDO, TDI, TMS. |
RF front end
The AD9361 shares two receive chains and one transmit chain with the outside world through a switched filter bank and a set of RF transformers.
| Ref | Part | Function |
|---|---|---|
| U2 | AD9361BBCZ | RF Agile Transceiver — 2×2 MIMO, integrated fractional-N synthesizers, 12-bit ADCs/DACs, tunable analog and digital filters. |
| T1, T2, T3 | TCM1-63AX+ | RF transformers (baluns) converting the AD9361's differential RX2/RX1/TX ports to single-ended signals for the filter and switch network. |
| U16, U19 | SKY13418-485LF | RF switches selecting the active band's filter path for each receive chain. |
Each band is realized as a pair of Mini-Circuits LC filters (a high-pass plus a low-pass section forming a band-pass), switched in and out per receive chain by the SKY13418 RF switches. The TX2 output bypasses the switched bank entirely, using a single fixed low-pass filter (LFCN-1400+) for simple wideband transmit.
Memory & storage
| Ref | Part | Function |
|---|---|---|
| U3, U4 | MT40A256M16 DDR4 | Two DDR4 SDRAM chips forming the PS-attached system memory — roughly 1 GB total. |
| U34 | MT25QU256ABA1EW7 | 256 Mbit QSPI NOR flash — primary boot device for the MPSoC. |
| J1 | microSD slot (TF-SD) | Removable-card boot / storage option. |
| U39 | TXS02612RTWR | Voltage-level translator between the SD card's 3.3/1.8 V I/O and the MPSoC's SD controller. |
| U30 | TPS51200 | DDR4 VTT/VREF termination regulator. |
Wireless, networking & GNSS
| Ref | Part | Function |
|---|---|---|
| U29 | ESP32-D0WDQ6-V3 | Wi-Fi / Bluetooth co-processor — an independent MCU + radio, bridged to the MPSoC over UART for network connectivity or out-of-band control. |
| U27 | DPX165950DT-8060A1 | 2.4 GHz / 5 GHz diplexer feeding the ESP32's dual-band antenna port from the WF SMA connector. |
| U25 | MAX-M8C-0 (u-blox) | Concurrent GNSS receiver — GPS, GLONASS, Galileo and BeiDou — providing position and a PPS timing reference. |
| U6 | RTL8211E-VB | Gigabit Ethernet PHY transceiver. |
| U7 | HR911130C | RJ45 jack with integrated magnetics and status LEDs. |
| U42 | CH334P | USB hub controller — splits the single USB-C port into multiple internal USB endpoints. |
| U41, U43 | CH340E ×2 | USB-to-UART bridges, exposing the ESP32 console and the MPSoC PS debug UART as two separate virtual COM ports. |
Clocking
A clean, adjustable reference clock matters more for an SDR than almost any other subsystem — frequency and phase noise on this line set a hard ceiling on RF performance.
| Ref | Part | Function |
|---|---|---|
| X5 | 40 MHz VCTCXO | Voltage-controlled temperature-compensated crystal oscillator — the master RF reference clock for the AD9361. |
| U45 | LTC2630ACSC6-HZ12 | 12-bit DAC that trims the VCTCXO's control voltage for fine frequency calibration. |
| U46 | CDC3RL02YFPR | Low-jitter clock buffer, fanning the reference clock out to the MPSoC and other clock consumers. |
| X2 | 33.33 MHz active oscillator | MPSoC PS reference clock. |
| X1, X3, X6 | 25 / 48 / 12 MHz crystals | Local reference clocks for the ESP32, USB hub, and USB-UART bridges respectively. |
Power architecture
A single 12 V input is stepped down and regulated into more than a dozen individual rails feeding the MPSoC core, RF analog circuitry, DDR4, and I/O domains separately.
Bring-up & debug interfaces
BATMAN-adv & OpenWiFi bring-up
Two separate layers get confused a lot, so it's worth being precise about which is which before flashing anything.
wlan0/sdr0 interface. For a true wireless MANET over this board's RF front end, you need OpenWiFi (or an equivalent mac80211 driver) running first, with BATMAN-adv attached to the interface it creates.
This is a custom carrier board, not one of Analog Devices' own listed reference designs — so there is no prebuilt "ADI Kuiper Linux" image for it. Kuiper only ships pre-built boot files for ADI's specific supported hardware projects (Zedboard, ZC706, ADRV9361-Z7035, ZCU102+FMCOMMS, ADALM-Pluto, etc.) — this board's own MPSoC part, DDR4 layout, and AD9361 wiring aren't among them, so a stock Kuiper .img is unlikely to boot correctly here.
Two realistic paths:
- Ask the board vendor for a PetaLinux/Yocto BSP or pre-built SD image for this specific design — if one exists, it's by far the fastest and safest route.
- Build your own PetaLinux/Yocto image targeting this MPSoC, using Analog Devices'
hdlandlinuxrepositories as a starting point for the AD9361 driver, then adapting the device tree to this board's actual DDR4 parts, RTL8211E PHY, and pin mapping.
Either way, boot from the microSD card first (set the SW2 DIP switch to the SD boot position — see Bring-up & Debug above). SD boot never touches the onboard QSPI flash, so a bad image just means reflashing the card, not recovering bricked hardware.
BATMAN-adv has shipped in the mainline Linux kernel since 2.6.38 — no ADI- or board-specific patch is required. As long as your kernel was built with CONFIG_BATMAN_ADV=m (the default in most Yocto/PetaLinux and Debian kernel configs), the module is already there.
# Install the userspace control tool apt update && apt install -y batctl build-essential # Load the kernel module modprobe batman-adv # Attach it to an existing network interface — eth0 works today, # over the board's RTL8211E Gigabit Ethernet port, for bench testing batctl if add eth0 ip link set up dev bat0 # Expected output when a second node is reachable: batctl n → lists discovered mesh neighbors
This proves BATMAN-adv itself works, but it's routing over a wired link — it isn't yet the wireless MANET. For that, batctl if add needs to point at a wireless interface instead of eth0, which is what Step 3 provides.
OpenWiFi (open-sdr/openwifi) is an open-source IEEE 802.11a/g/n baseband — part FPGA logic, part Linux driver — that makes the AD9361 behave like a normal mac80211 Wi-Fi card. It officially supports six specific reference platforms:
- Zedboard + FMCOMMS2/3/4
- Xilinx ZC706 + FMCOMMS2/3/4
- ADRV9361-Z7035 SOM + ADRV1CRR-BOB carrier
- ADRV9361-Z7035 SOM + ADRV1CRR-FMC carrier
- Low-cost Zynq-7020 + AD9361 board
- ZCU102 (Zynq UltraScale+) + FMCOMMS2/3/4
This board isn't one of them — it has an onboard AD9361 wired directly to the MPSoC rather than an FMC daughtercard, so getting OpenWiFi running here means porting it: retargeting the openwifi-hw Vivado project to this MPSoC part number and this board's specific AD9361 LVDS/GPIO pin mapping, building a new bitstream, and following their published porting guide. Several hobbyist boards with an onboard (non-FMC) AD9361 and a Zynq-7020 — ANTSDR, the HamGeek P210, LibreSDR — have done exactly this kind of port successfully, so it's a realistic project, just not a "flash an image and go" one on unlisted hardware.
# 1. Get the FPGA and driver source git clone https://github.com/open-sdr/openwifi-hw git clone https://github.com/open-sdr/openwifi # 2. Follow the README's porting guide to add a new board target # under openwifi-hw/boards/ — matching this MPSoC part number # and the AD9361 LVDS/control pin mapping from the schematic # 3. Build the bitstream in Vivado, export hardware + device tree, # then build the openwifi Linux image from scratch per their guide # 4. Once booted, OpenWiFi brings up a standard wireless interface: sdr0 → appears exactly like any other mac80211 Wi-Fi card
Once OpenWiFi is running and sdr0 exists, point BATMAN-adv at it instead of Ethernet, and optionally bridge both together so wired and wireless clients share the same mesh:
# Attach BATMAN-adv to the OpenWiFi radio interface instead of eth0 modprobe batman-adv batctl if add sdr0 ip link set dev sdr0 up ip link set dev bat0 up # Optional: bridge the mesh with the wired Ethernet port too ip link add name br0 type bridge ip link set dev eth0 master br0 ip link set dev bat0 master br0 ip link set dev br0 up